Modern computers frequently are constructed to permit user programs to execute code and fetch data from virtual memory addresses. However, data and memory modules must still be addressed with physical addresses. Therefore, hardware tables are used to translate virtual addresses into physical addresses. Such a hardware table is called a Virtual Address Translation Table (VATT).
In order to improve the efficiency of virtual to physical address translation, the VATT can include a section of high speed register memory of sufficient speed to execute instructions within a single processor cycle. Such a VATT is typically located at or near a high speed memory portion of the computer processor, in which memory is stored the most recently used address translation entries. This high speed memory section is referred to as a Translation Look-aside Buffer (TLB). Frequently, as programs progress, address translations will be found in the TLB, thus speeding up program execution. However, when an address translation is needed which is not in the TLB, a new table entry must be fetched by hardware from the VATT and loaded as an entry into the TLB.
Methods have been developed to increase the speed with which the TLB entries can be updated. One such method is the use of a simple organization of the entries within the VATT. For example, the VATT can be a simple table of sequential virtual memory addresses or a simple, hierarchical extension of a sequential table as explained in "Computer Structures: Principles and Examples" by D. Siewiorek, C. Bell, and A. Newell, McGraw Hill, 1982, pp. 227-243. Such simple organizations reduce the complexity and cost of the TLB fetch hardware, but significantly limit the structure of addresses within the VATT. More complex VATT formats are desirable because the virtual memory address space may be significantly larger than the actual physical address space implemented in hardware. Thus, the size of the sequential virtual address tables or the hierarchical structures containing such tables can exceed the size of the physical memory. The system must then swap portions of the tables between the physical memory and an alternate slow memory device such as a disc when access to entire table is required.
A more scalable approach is the use of hashing functions as described in "Translating a Large Virtual Address" by M. Houdek, G. Mitchell, IBM System 38 Technical Development, IBM GS80-0239, 1978, pp. 22-25 to translate virtual addresses in the TLB to physical addresses in the VATT. A hashing function is a pseudo-random method for efficient searching of the VATT for a translation table entry. Although the use of hashing functions is a flexible method for searching the VATT entries, it typically degrades the speed of the search, or increases the cost of TLB fetch hardware.